tm data device corporation 105 wilbur place bohemia, new york 11716 631-567-5600 fax: 631-567-7358 www.ddc-web.com for more information contact: technical support: 1-800-ddc-5757 ext. 7382 features ? 16-bit resolution pin programmable gain control two channels in one 36-pin ddip accuracy to 2 min. 0.1% scale factor variation with angle dc-coupled reference high reliability cmos d/r chip 8-bit/2-byte double-buffered transparent latches description the drc-11522 is a dual 16-bit digital-to-resolver (d/r) converter. each channel is independent from the other with the exception of the 16 digital lines. the drc-11522 allows the user to program the gain of the resolver output. packaged in a 36-pin double dip, the drc-11522 is two digital-to- resolver converters in one hybrid module. using an ac reference input, the drc-11522 is a digital-to-resolver converter. when using a dc reference input, the unit can be used as a hybrid digital-to-sin/cos dc converter. with the reference input proportional to the radius vec- tor, the drc-11522 converts polar to rectangular coordinates. the circuit design in the drc-11522 allows for higher accuracy and reduces the output scale factor variation so that the output can drive displays directly. the output line-to-line voltage can be scaled by pin programming. other features include buffered reference input, and a wide operating temperature range. applications because of its high reliability, small size and low power consumption, the drc-11522 is ideal for the most stringent and severe industrial and military ground or avionics applications. all units are available with mil-prf-38534 processing. among the many possible applications are computer-based systems in which digital information is processed, such as simulators, flight trainers, flight instrumentation, fire control systems, radar and navi- gation systems. ? 1988, 1999 data device corporation drc-11522 two-channel digital-to-resolver converter make sure the next card you purchase has...
2 data device corporation www.ddc-web.com drc-11522 rev. j figure 1. drc-11522 block diagram output amplifiers d/r converter high accuracy low scale factor variation transparent latch transparent latch transparent latch transparent latch d/r converter high accuracy low scale factor variation output amplifiers reference conditioner ref cos a sin a - + gc1-a gc2-a la-a lm-a +c +s +c +s cos b sin b reference conditioner ref gc1-b gc2-b lm-b la-b ll-a ll-b digital input +15 v -15 v gnd - +
3 data device corporation www.ddc-web.com drc-11522 rev. j table 1. specifications (for each channel) apply over temperature range, power supply ranges, reference voltage, and frequency range, and 10% harmonic distortion in the r eference. parameter value description/remarks resolution 16 bits (0.33 arc minutes) msb = 180 lsb = 0.0055 accuracy output accuracy differential linearity radius accuracy 4 minutes to 2 minutes + 1 lsb (see ordering info) 1 lsb max 0.03% accuracy applies over operating temp. range simultaneous amplitude variation in both outputs as a function of digital angle dynamics output settling time less than 20 sec for any digital step change. for any analog or digital step change digital input logic type logic ?0? logic ?1? load current -0.3 vdc to 1.25 vdc +2.0 vdc to +5.5 vdc 20 a max to gnd 20 a to v l natural binary angle parallel positive logic cmos and ttl compatible. inputs are cmos transient protected. each input has a 20 a max pull down to gnd. external logic voltage not needed. ttl compatible. bits 1-16 ll , lm , la (see timing diagram, figure 2) reference input type frequency range voltage input impedance dc to 1000 hz 3.5 v 10% 10 m ohm min programmable (see table 2.) dc to 10 khz with reduced accuracy. 0 to 10 peak ac or dc operational amplifier buffer analog output type output current max output voltage (tracks reference input voltage) converter gain (k) transformation ratio tol. scale factor variation dc offset 2 ma rms max k * v in * sin also k * v in * cos 0.5, 1.0, or 2.0 1% 0.2% max 0.1% max 10 mv typical, 25 mv max power supplies voltage max voltage without damage current or impedance 15 vdc 10% 18 vdc 40 ma max for 10 v peak output temperature ranges (case) operating -1 option -3 option storage -55c to +125c 0c to +70c -60c to +135c physical characteristics type size weight 36-pin double dip 0.78 x 1.9 x 0.21 inch (2.0 x 4.8 x 0.53 cm) 0.6 oz (17g) max resolver 10 v peak ac or dc see table 2. each line to gnd
4 data device corporation www.ddc-web.com drc-11522 rev. j technical information digital inputs for each channel, the 16-bit digital angle is double buffered with transparent latches (see figure 1). the latch controls have internal pull-up current sources to +5 v, this puts the latches in the transparent mode when they are not connected. the angle is determined by adding the logic bits. the enable inputs are ll (1st latch lsbs), lm (1st latch msbs), and la (2nd latch all); see figure 2 for timing. output scaling and reference level adjustment the drc-11522 operates like a multiplying d/a converter in that the voltage of each output line is directly proportional to the ref- erence voltage. the maximum line-to-line levels are determined by the output amplifiers and are programmable for a gain of 0.5, 1.0, or 2.0 (see table 2.). output phasing and output scale factor the analog output signals have the following phasing: sin = (ref * k) a o [1 + a( )] sin cos = (ref * k) a o [1 + a( )] cos the output amplifiers simultaneously track reference voltage fluctuations because they are proportional to (ref * k). the transformation ratio a o is determined by the programmable gain inputs (0.5, 1.0, or 2.0). the maximum variation in a o from all causes is 0.1%. the term a( ) represents the variation of the amplitude with the digital signal input angle. a( ), which is called the scale factor variation, is a smooth function of ( ) without dis- continuities and is less than 0.1% for all values of ( ). the total maximum variation in a o [1 + a( )] is therefore 0.2%. because the amplitude factor (ref * k) a o [1 + a( )] varies simultaneously on all output lines, it is not a source of error when the drc-11522 is driving a ratiometric system. however, if the outputs are used independently, as in x-y plotters, the amplitude variations must be taken into account. table 2. programmable gain gc1-a (pin 7) gc2-a (pin 8) gain (k) gnd open open open gnd open 0.5 1.0 2.0 gc1-b (pin 4) gc2-b (pin 5) gain (k) table 3. pinouts pin function pin function 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 ll -b cos a sin a gc1-b gc2-b ref b gc1-a gc2-a ref a cos b sin b nc +15 v -15 v la -b la -a ll -a gnd 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 bit 16 (lsb) bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 (msb) lm -a lm -b note: functions ll , lm , la both a and b may be left unconnected when not used. table 4. pin definitions pin definition gnd b1-b16 lm -a lm -b ll -a ll -b la -a la -b +15 v -15 v ref-a ref-b gc1-a gc2-a gc1-b gc2-b sin a cos a sin b cos b power supply ground digital ground analog signal ground digital input bits, b1 = msb = 180 degrees high byte enable (b1-b8) for msb?s 8-bit input register of channel a. logic high enables, low holds. high byte enable (b1-b8) for msb?s 8-bit input register channel b logic high enables, low holds. low byte enable (b9-b16) for lsb?s 8-bit input register of channel a. logic high enables, low holds low byte enable (b9-b16) for lsb?s 8-bit input register of channel b. logic high enables, low holds. channel a load converter. logic high transfers channel a input registers data into 16-bit holding register. when low, channel a is in hold mode. channel b load converter. logic high transfers channel b input registers data into 16-bit holding register. when low, channel b is in hold mode. power supply voltage. power supply voltage. caution: reversal of power supplies will damage the converter. channel a reference voltage input channel b reference voltage input channel a gain programming pin channel a gain programming pin channel b gain programming pin channel b gain programming pin analog output of channel a analog output of channel a analog output of channel b analog output of channel b
5 data device corporation www.ddc-web.com drc-11522 rev. j 1.895 0.005 (48.1 0.13) 1.700 0.005 (43.2 0.13) 0.018 (0.46) diam typ 0.100 typ(2.54) tol. non- cumulative 0.21 max (5.3) dot identifies pin 1 0.775 0.005 (19.7 0.13) 0.600 0.005 (15.2 0.13) 0.09 0.01 (2.3 0.25) 0.10 0.01 (2.5 0.3) side view bottom view 0.25 min (6.4) 0.015 max (0.39) seating plane 0.055 (1.4) rad typ 0.086 typ radius figure 3. drc-11522 mechanical outline (36-pin double dip) notes: 1. dimensions shown are in inches (millimeters) 2. lead identification numbers are for reference only. 3. lead cluster shall be centered within 0.010 (2.54) of outline dimensions. lead spacing dimensions apply only at seating plane. 4. pin material meets solderability requirements of mil-std-202e, method 208c. 5. package is kovar with electroless nickel plating. 6. case is electrically floating. 200 ns min. latched data 1-16 bits 100 ns min. 50 ns min. transparent figure 2. ll , lm , and la timing diagram
6 data device corporation www.ddc-web.com drc-11522 rev. j ordering information drc-11522-xxxx supplemental process requirements: s = pre-cap source inspection l = pull test q = pull test and pre-cap inspection k = one lot date code w = one lot date code and precap source y = one lot date code and 100% pull test z = one lot date code, precap source and 100% pull test blank = none of the above accuracy: 3 = 4 minutes + 1lsb 4 = 2 minutes + 1lsb process requirements: 0 = standard ddc processing, no burn-in (see table below.) 1 = mil-prf-38534 compliant 2 = b* 3 = mil-prf-38534 compliant with pind testing 4 = mil-prf-38534 compliant with solder dip 5 = mil-prf-38534 compliant with pind testing and solder dip 6 = b* with pind testing 7 = b* with solder dip 8 = b* with pind testing and solder dip 9 = standard ddc processing with solder dip, no burn-in (see table below.) temperature grade/data requirements: 1 = -55 c to +125 c 2 = -40 c to +85 c 3 = 0 c to +70 c 4 = -55 c to +125 c with variables test data 5 = -40 c to +85 c with variables test data 8 = 0 c to +70 c with variables test data *standard ddc processing with burn-in and full temperature test (see table below). ? 1015, table 1 burn-in a 2001 constant acceleration c 1010 temperature cycle a and c 1014 seal ? 2009, 2010, 2017, and 2032 inspection condition(s) method(s) test mil-std-883 standard ddc processing
7 data device corporation www.ddc-web.com drc-11522 rev. j notes
8 j-08/01-250 printed in the u.s.a. the information in this data sheet is believed to be accurate; however, no responsibility is assumed by data device corporation for its use, and no license or rights are granted by implication or otherwise in connection therewith. specifications are subject to change without notice. 105 wilbur place, bohemia, new york 11716-2482 for technical support - 1-800-ddc-5757 ext. 7382 headquarters, n.y., u.s.a. - tel: (631) 567-5600, fax: (631) 567-7358 southeast, u.s.a. - tel: (703) 450-7900, fax: (703) 450-6610 west coast, u.s.a. - tel: (714) 895-9777, fax: (714) 895-4988 united kingdom - tel: +44-(0)1635-811140, fax: +44-(0)1635-32264 ireland - tel: +353-21-341065, fax: +353-21-341568 france - tel: +33-(0)1-41-16-3424, fax: +33-(0)1-41-16-3425 germany - tel: +49-(0)8141-349-087, fax: +49-(0)8141-349-089 japan - tel: +81-(0)3-3814-7688, fax: +81-(0)3-3814-7689 world wide web - http://www.ddc-web.com data device corporation registered to iso 9001 file no. a5976 r e g i s t e r e d f i r m ? u
|
